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Nanotech Research Ideas I Wished I Could Carry Out
Initial Note: I believe all Focuses are equally as important despite Focus 1 having more detail. I
am writing this doc as if to address anyone in the global general public who remembers Ohm’s
law (I=V/R=GV), has at least high school level knowledge of biology and math, and has access
to a search engine. Any professors or researchers who miraculously read this will have to bear
with me. While those in the field will definitely understand better, since memristors and
neuromorphic computing are still subjects never mentioned in a classroom setting at the majority
of electrical engineering and computer science departments around the world, I believe anyone
who is patient enough to read through some terminology (there is A LOT of terminology) will be
able to grasp the underlying fundamental ideas discussed just as well as some “experts”. Some
may tell you otherwise but in my opinion, don’t be intimidated by fancy words. Most college
courses exist to just equip you with terminology but nowadays there are plenty of good internet
explanations, so again, I truly believe even someone from the general public who fits the criteria
above will be able to understand the core ideas. Throughout this doc, I have dropped hints for a
sub 5-nm thick device (hidden idea) that I’m confident would succeed in industry but require
some novel fabrication technologies, which are very possible to create and optimize within the
next 5-10 years if resources are allocated efficiently. Though, this probably won’t be the case or
else I wouldn’t have k*ll*d myself. I’ll leave it up to you to try and figure out the device and
fabrication process, however, I wholeheartedly believe whichever company or nation manages to
experimentally realize the hidden idea first will make TSMC’s fabrication facilities, Nvidia’s
GPU hardware, and IBM’s overhyped quantum computing initiative obsolete. I have also left a
collection of some of the papers I have read through for the past four years on an SSD I am
leaving to my parents, that may be helpful in realizing the hidden idea (though I do not think it’s
absolutely necessary). I have requested my parents allow anyone who asks and has a sound mind
to receive a copy of all files contained in the SSD on the one in a billion chance someone is
curious enough. However, this idea also has the potential to start a new era of warfare (probably
not in the way the vast majority imagine AI warfare), so I’m hoping on the off chance someone
actually reads this entire document and manages to figure out the hidden idea, they will also be
smart enough to only use it for humanity’s benefit. Of course, I understand if all of you think I’m
full of crap considering I do not have any tangible research results of my own experiments and
am just some idiotic undergrad eager for attention, but even if you give this a quick 5 minute
skim, I’ll be satisfied knowing at least a small part of my work is proven to have existed, even
when I as a person will be forgotten. These ideas are presented without figures since I have no
idea how they’ll affect the pdf upload on the various places this is posted. Plus, I’m writing this
in one sitting so I did away with all formalities and proper grammar usage. I mention a few
papers and key terms such as STDP or CBRAM which can be searched online and the papers I
mention are open access. Before discussing my ideas, I made the first half of this doc as a
summary of my interpretation on what a memristor is and how memristor crossbar arrays
perform in-memory computing via SNNs. I think it’s also worth noting that I never once refer to
technology nodes and just refer to the combined 3-layer thickness of memristors at times. This is
because tech nodes in modern day fabrication technology don't reflect an individual device’s
actual size. Intel’s “20Å” GAAFET campaign is just marketing and does NOT mean individual
devices are 2 nm long in any particular spatial dimension. Otherwise it would have to break the
laws of physics to even operate. Nodes used to be based on half-pitch distances but everyone
keeps coming up with different device geometries so now it’s actually meaningless.
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What is a memristor and how do they work?
The memristor, first proposed by Leon Chua in 1971 and physically realized by Hewlett
Packard Labs (HP Labs) in 2008, is among the best candidates for next generation non-volatile
data storage/processing, edge computing, and artificial intelligence (AI) hardware. Other
alternative memory candidates that are also decent are phase change memory and ferroelectrics.
Memristors have recently become an even more popular area of research due to the rising
influence of large language models such as ChatGPT. First I’ll explain how an individual device
works, then memristor mechanisms, followed by crossbar arrays, and finally how memristors
achieve in-memory computing. I have also interjected my personal opinion at certain points to
express my distaste for the way some of the current literature on memristors and neuromorphic
computing is written.
Memristors are two-terminal devices that have the ability to “remember its resistance”
upon a voltage bias. The popular vertical configuration MIM design (metal / insulator / metal)
consists of a resistive switching (RS) layer sandwiched between top and bottom electrodes (TE
and BE). Because of their simple device structure and lack of tunneling leakage, memristors can
be miniaturized further than conventional transistor (CMOS) technology. In its initial
configuration, the RS layer is in a high resistance state (HRS)/low conductance state i.e. the
output current in this state can be interpreted as a logical 0 in digital circuits. When a certain set
voltage, V
set
, is applied across the electrodes the RS layer switches to a low resistance state
(LRS)/high conductance state i.e. output current in this state can be interpreted as a logical 1 in
digital circuits. The device can return to the HRS by applying enough voltage of opposite
polarity, V
reset
(technically this is considered a “bipolar” memristor. There are also “unipolar”
memristors however, why some devices are unipolar and some are bipolar has yet to be fully
worked out). This resistive switching results in the memristor’s characteristic pinched hysteresis
current-voltage relationship. Some argue that Chua’s original idea of a memristor has yet to be
realized but Chua once famously stated, “if it’s pinched, it’s a memristor”, i.e. if a two terminal
device exhibits a pinched I-V hysteresis loop upon voltage sweep (AC or DC), then it is a
memristor regardless if it fits the exact theoretical definition proposed in 1971. Memristors
explored are able to maintain these resistance states for a decent amount of time (known as
retention) after powered off (non-volatile data storage) and have demonstrated the ability to
switch back and forth between resistance states many times (number of bit rewrite cycles known
as endurance). Some memristors are capable of multi-level switching i.e. can achieve multiple
resistance states and therefore store more than 1 bit. 2
n
resistance states are needed to store
n-number of bits. To read out a bit, a voltage of lower magnitude than V
set
, V
read
is applied and
the resulting current gives us the bit readout. Unfortunately, few memristors discussed in
literature produced by universities display good retention, endurance, bit writing and reading
speeds, and low switching voltages, all together (maybe hidden for proprietary reasons?),
however, devices can be optimized to meet industry standards. I think research groups just don’t
bother because they would rather milk as many papers as possible out of each individual device
to increase their h-index, which is kinda a questionable metric to begin with.
There are several mechanisms behind memristor conduction but there are two main ones
that dictate the way most memristors behave. One is the V
set
triggered filamentation of either
metal atoms or oxygen vacancies, or sometimes vacancies of other atoms, within the initially
insulating material (providing path for electrons and setting device in LRS). When filaments are
formed from metal atoms through a redox reaction on active electrode surfaces such as Cu or Ag,
the device is referred to as conductive bridge random access memory (CBRAM; also referred to
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as ECM i.e. electrochemical metallization). When they are formed through oxygen vacancies the
device is referred to as metal oxide resistive memory (OxRAM; also referred to as VCM i.e.
valence change mechanism). Many OxRAM are also non-filamentary and oxygen vacancies
disperse throughout the insulating material instead of forming filaments, resulting in SCLC
mechanism of transport in many cases. When V
reset
is applied, filaments rupture and metal atoms
and vacancies return to the initial state (HRS) due to electrostatic repulsion and Joule heating.
The other notable mechanism is space charge limited current/conduction (SCLC), though
honestly, a lot of papers that claim SCLC for their device absolutely suck at explaining how it
works and simply write down Child’s law with basically no context. Personally, I find this
mechanism not as straightforward to understand as filamentation since it’s hard to visualize, but
if you look up “SCLC Yifan Yuan” and click the pdf link from the University of Nebraska -
Lincoln, you can find a decent explanation. Thank you for your service Yifan. But unfortunately,
things are still complicated because some claim their device conducts through an SCLC
mechanism in either the HRS or LRS and through a different transport mechanism in the other
resistance state (sometimes Schottky emission), which is something I’ve always been confused
about because the way people claim electron transport occurs in the other resistance state in a
device that displays SCLC feels very hand wavy. Or maybe I’m just too stupid. Mechanisms and
RS ability depend on material choices/properties including RS layer composition and work
function difference between electrodes. For space, I’ll not delve more because it requires
rigorous semiconductor physics/thermodynamics and understanding of materials science, which
is not inherently necessary for just knowing how memristors operate as memory devices.
One reason why memristor research gained traction is the prospect of being able to
perform “neuromorphic” or “in-memory” computing, which involves simultaneously storing and
processing data. Current von-Neumann architecture involves storage and processing being
performed in separate parts of a computer chip and data having to be transferred between storage
(V-NAND SSDs, DRAM, VRAM, SRAM) and processing centers (CPU, GPU, TPU), which
consumes significant energy and time i.e. latency AKA the von-Neumann bottleneck. In-memory
computing is inspired (key word: inspired!) from the way the human brain processes information
in hopes that we emulate the incredibly low power consumption the brain achieves. For context,
data centers globally consumed around 400-500 TWh in 2022 but are projected to go past 1000
TWh in 5 years. The total energy produced by all nuclear power plants combined that same year
was around 2500 TWh so as demand driven by AI increases, we may run into some problems
(and I’m not sure this statistic accounts for cooling system maintenance). Granted, this is still I
think like 5% of the power grid, but being able to redirect even half of that 5% for something
else can still have significant societal impacts.
With memristor crossbar arrays, data inputs take on the form of a vector of applied
voltages and it performs matrix multiplication to get a vector of current outputs that depend on
the conductance of each memristor in the array (Ohm’s law). Each individual memristor can be
set to a particular conductance by applying appropriate voltages along TE and BE. The crossbar
array acts as an adjustable weighing matrix, like with other neural networks, but the advantage is
each individual memristor can correspond to a weight (conductance = weight value) under the
right form of inputs. With CMOS tech, one weight needs many transistors if we want high
precision values, which is actually being sacrificed in Nvidia’s recent Blackwell chip. For those
who may not have theoretical understanding or practical experience with neural networks, I
recommend checking out the youtube channel 3blue1brown which gives a nice, easily accessible,
surface level overview on what neural networks are and how they are trained, covering topics
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such as perceptrons, optimization algorithms, convolutions, and backpropagation. Anyway, if we
solely use DC voltage sources to set the conductance of each memristor in an array to either HRS
or LRS, the net current output at the end of each row of memristors can take on a large set of
discrete values, with more values being possible as arrays increase in size. If an array has enough
rows and columns, one could argue the weights can be tuned in a continuous manner (can take
on a range of continuous values) with each row representing a weight. However, each individual
memristor is capable of taking on a continuous range of weights under analog conditions. Most
claim that memristors become more advantageous when operated in an analog fashion by
inputting voltage pulses (spike trains) generated by an AC voltage source in order to set
memristor weight values. The weight is tuned in a continuous manner based on the time
difference between the spikes received at the TE (presynaptic spike) and BE (postsynaptic
spike). This adds a temporal component (time based, everyone in the literature loves using the
word temporal though because it makes them sound smart) when training the network for AI
applications. This type of learning network is known as a spiking neural network (SNN).
Memristors are “in-memory” in the sense that the memristor is capable of both storing weights
(memory) and processing incoming data streams based on those weights i.e. memory and
processing happens within the same device/location.
In SNNs, when the presynaptic pulse precedes the postsynaptic pulse (positive spike
timing delay), conductance will gradually increase and this is called long term potentiation
(LTP). When the postsynaptic pulse precedes the presynaptic pulse (negative spike timing delay),
the conductance will gradually decrease i.e. long term depression (LTD). This behavior together
is known as STDP (spike timing dependent plasticity). Some papers claim that increasing the
number of positive voltage pulses at constant frequency on one electrode results in LTP and
increasing the number of negative voltage pulses to the same electrode results in LTD, and as a
result they have achieved STDP. This still accomplishes the same end goal of gradually changing
conductance I guess, however, it is questionable to still call this STDP given these types of
experiments are not implementing true postsynaptic spikes (only applying pulse trains on one
electrode instead of two). Honestly, because of this discrepancy I question at times whether I
fully understand the way STDP works in memristors despite fully understanding how it works in
the context of biological neurons. This could be due to the confusing way most papers present
LTP and LTD curves, as well as the lack of specification for how spike trains are applied and
whether or not they are applied to both electrodes. Modulating spike pulse width and spike
frequency changes the extent to which conductance is increased or decreased, but this
modulation may result in increased time required to train an SNN, hence, the motivation for
Focus 2. The use of neuroscience terminology comes from the fact that many compare this
behavior to the way the human brain processes information. But remember it is NOT the same as
the human brain, just inspired and fitted to a particular model i.e. Hebbian theory, which is
actually over 70 years old. Technically, if you want to get into the nitty gritty details, there are 4
different types of Hebbian learning a device could display (symmetric/asymmetric and
anti-Hebbian versions) but you can sum up the most common type, asymmetric Hebbian
learning, with the following statement: “neurons that fire together, wire together” (Donald Hebb,
1949). Regardless of memristors only being based on a specific model of the way the brain
works, you will see memristors/RS layers referred to as “synapses” and the two terminal
electrodes referred to as “presynaptic neurons” and “postsynaptic neurons”. The literature is
littered with side by side images of a memristor symbol next to a diagram of two neurons
communicating with each other, which I personally find annoyingly unhelpful in learning how
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in-memory computing in memristors actually works, but researchers stick it in there because it
pads space with cool looking figures.
Meanwhile, conventional CMOS based neural nets need many transistors for updating a
single weight, wasting hardware space and consuming a significant amount of energy. Crossbar
arrays also have the great advantage of being CMOS compatible (can be stacked right on top of a
transistor array) and are vertically stackable, so we can increase data density in a similar fashion
as V-NAND SSDs. One drawback holding memristor crossbar arrays back from truly entering
industry is a problem known as “sneak path current”, where the current output of one memristor
during encoding affects the current output of its neighbors. This causes reliability issues and is
being addressed in two different ways. The first is through the addition of a “selector” material to
isolate the memristor being encoded with a pulse train, known as the 1S1R design. The second
(and probably more popular) method to isolate encoded memristors involves connecting each
memristor to a corresponding transistor known as the 1T1R design. Some even combine
transistor and memristor functions into one device (many voltage terminals) known as a
memtransistor, however, the only true memtransistors I know of that exist are based on the 2D
material MoS
2
, which results in designs limited to lateral configurations due to MoS
2
fabrication
constraints. Another drawback that affects reliability is device to device variation in V
set
and V
reset
which few papers addressed. Fortunately, this is a problem that can be addressed through
optimizing the fabrication process, but it is still something that exists that only half of memristor
papers out there address.
It is argued in many papers that SNNs are ideal for analog computing, however, to
interface with other technologies and for pulse generation, ADCs and DACs are necessary which
creates overhead that makes the energy saving property of an SNN pointless and limits
applications for memristor crossbar arrays. Plus, I can’t really find any literature that actually
goes through with some sort of image recognition task with purely analog inputs. Most just use
standard chopped DC pulse train inputs and then in their conclusions state that their device is a
stepping stone for analog computing, which makes no freaking sense to me (or maybe I lack
understanding). This is never really brought up much within the memristor community for some
reason and everyone pretends that using purely DC inputs and performing no AC frequency
response analysis is good enough. Therefore, to make memristors that will actually be useful for
real life applications, I have proposed Focus 1 to give industry incentive for memristor
technology from a fabrication standpoint, and Focuses 2 and 3 as incentives for memristor tech
from an application/analog computing standpoint where the bang might be worth the buck. I
have also included a miscellaneous focus on a potential ferroelectric device (not a memristor).
Ferroelectrics work similar to magnetic-tape data storage and hard drives except instead of
tuning the direction of a magnetic dipole upon a magnetic field, these devices work by tuning the
direction/polarization of an electric dipole upon an electric field/applied voltage, resulting in a
characteristic current-voltage hysteresis loop. Finally, a random thought I think is also worth
mentioning is that peripheral CMOS circuitry is usually needed in addition to memristor crossbar
arrays in order for running computations. However, it would be interesting if memristors with
incredibly high ON/OFF ratios (ratio between resistance in HRS and resistance in the LRS) and
fast enough read/write times could replace all the transistors in this peripheral circuitry.
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Focus 1: Highly Scalable Biomolecular Memristor Devices with Cheap and Green
Production Processes (Approaches listed in order of priority)
The overall end goal is to fabricate a biomolecular memristor (or biomemristor i.e. memristor
with biological material as RS layer) chip that meets industry standards through solution
processes (bioconjugation, printing techniques, surface chemistry) with ingredients being
produced by bacteria in a continuous bioreactor (inspired by industrial Insulin production).
Electrodes would start out being fabricated through conventional means with conventional metal
materials (PVD/lithographic patterning) but then as organic or carbon nanotube (CNT) electrodes
increase in quality, transition to a fully organic device. If printing technologies ever manage to
achieve nanometer scale resolution (while maintaining scalability) and sub-50 nm film thickness,
then the overall production process could be performed through additive fabrication and solution
processing, making expensive lithographic techniques obsolete and starting an era of continuous
flow manufacturing of nanoelectronics. Approaches are listed in order of priority, and all involve
proteins to serve as the RS layer. There are also biomemristors that use genetic material
(DNA/RNA), lipids, or carbohydrates (cellulose derivatives), but I’m biased towards protein
memristors because they seem to have the most success aside from cellulose based memristors
and I’ll be honest, I also just found protein chemistry more interesting (for all I know,
nitrocellulose nanocrystal memristors or devices incorporating carbs from the layers of an onion
may show just as much promise as my hidden idea). I believe the Azurin device has the greatest
potential to enter industry despite prior work on Azurin RRAM never being expanded. Of
course, lots of optimization needs to be done in order for the device to operate over a wider range
of temperatures and take on minimal damage from Joule heating since proteins are
environmentally sensitive. The sericin device is something I attempted in the past but was never
able to achieve due to lack of proper fab facilities and poor choice in protein purification method.
There is also a possibility that someone manages to make a fibroin device that outperforms all
the other biomemristors proposed given the extensive work already performed. However, there
are two main points of contention with all biomemristors: 1. Interfacing biomaterials with
inorganic surfaces can be kinda a pain and 2. When I said there are several mechanisms behind
memristors above, biomemristors are where that applies the most. Having different mechanisms
behind resistance switching may not hinder the actual device performance but it definitely slows
the thought process behind how to further optimize a device and some creativity is needed. For
all approaches, standard physical, chemical, and electrical characterization is needed (for both
RS layer, and the overall device at the end), followed by measurements demonstrating STDP
through proper measurement of LTP and LTD corresponding to realistic spike train inputs and
using SNNs for practical applications.
● Approach 1: Cu/Azurin Variant (bioengineered for optimal device properties in E. coli
expression system)/ITO (or TiN if surface modification feasible; both vertical devices)
- Advantages:
1. Azurin is a blue copper centered redox protein originating in
Pseudomonas aeruginosa (very common bacteria) that is thoroughly
characterized because of its potential anti-breast cancer properties. Has
interesting electron transport properties and beta-barrel structure.
2. Very small in size (14 kDa, 128 amino acids, ~3 nm in height depending
on adsorption orientation) allowing for small single molecule devices.
3. Previously demonstrated RRAM and transistor capabilities. A good start is
looking at Yagati et al. work (Korean Group) on Azurin-CdSe/ZnS QD
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“biohybrid” RRAM. There are also a few folks at IIT Delhi who submitted
a IEEE conference paper for Al/Azurin/ITO/PET device but its electrical
characteristics (retention, endurance, operating voltages, etc.) are pretty
crappy and the fabrication/experimental methods are kinda sketchy,
especially considering they do not specify how they made the Azurin
layer, which they claim is a single “6.2 nm monolayer”. Meanwhile, in a
Zhang et al. work (collaboration between Sun Yat-sen University in China
and Northwestern University) titled The dynamic conductance response
and mechanics-modulated memristive behavior of the Azurin monolayer
under cyclic loads, as well as other works show pretty thorough atomic
force microscopy (AFM) measurements that an Azurin monolayer is
around 3 nm in height/thickness.
4. Prior work has already shown Azurin can be expressed and mass produced
in E. coli. Because of its small size, variants of Azurin are relatively
simple to produce. For non-bio people, this refers to a protein that has an
alteration/mutation in its amino acid sequence. For example Phe114Pro
Azurin refers to Azurin that normally has phenylalanine as its 114th amino
acid (count starting at the N-terminus of the protein), but it was replaced
with Proline.
5. Based on the initial Azurin device and better understanding of
bioengineered Azurin electron transport, miniaturizing to a peptide
memristor on the order of 1-2 nm in thickness (incorporating 2D materials
such as MXenes or graphene as electrodes) may be a possibility.
- Disadvantages
1. Poole-Frenkel electron transport mechanism in ON state but speculation
that in crossbar array, Fowler Nordheim tunneling may impact overall
device output as in conventional charge trap memory devices (although,
this is purely speculative and may not be an issue).
● Approach 2: Al (or Cu)/Sericin (photocrosslinkable)/TiN (for lateral device; ITO for
vertical device)
- Advantages:
1. Can incorporate green UV lithography methods for patterning Sericin
structures since photocrosslinkable Sericin acts as a negative photoresist
(which can be developed in hot DI water unlike fibroin).
2. Sericin is highly biocompatible and has properties for use in chemical
sensing (ability to scavenge free radicals), drug delivery, wound healing,
and other biomedical applications (which is quite relevant considering all
the recent hype over Neuralink), so lateral Sericin RRAM devices may be
used for real time sensing and drug delivery.
3. Extraction process for Bombyx mori Sericin is simple (degumming i.e.
separating sericin from fibroin) and raw materials are incredibly cheap
since Sericin is a waste product of silk production. There are many works
on fibroin memristors but Sericin memristors have yet to be explored.
4. Sericin has been shown in many prior works to stabilize metal ions, more
specifically, Ag nanoparticles. Depending on whether the TE is inert or
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electrochemically active, sericin memristors may display either
filamentation or SCLC mechanism of electron transport.
- Disadvantages:
1. Silk source and the type of degumming process has effects on sericin
properties (could also be an advantage depending on application). There
are technically three different types of sericin (A, B, C) with different
levels of hydrophilicity and molecular weights, ranging from 20-400 kDa.
2. Mechanism of conduction in one of the two prior sericin devices
fabricated is implied to be based on charge trap defects throughout sericin
film i.e. SCLC (2013 Wang et al. Ag/Sericin/Au device). I’m honestly
confused as to what these defects consist of and why Ag filamentation
didn’t occur as predicted in advantage 4. Given the unclear nature of the
device, miniaturizing to sub-50 nm in thickness and still maintaining
functionality may be challenging.
3. Narrow pH and temp. range and not as much work in producing sericin
variants as Azurin. This combined with disadvantage 2 may limit sericin
devices to only biomedical applications, however, this still has a lot of
potential.
● Approach 3: Cu/Cytochrome nanowire monomer suspended in dielectric/TiN (or ITO)
- Advantages:
1. Geobacter sulfurreducens OmcS cytochrome nanowires are currently
under study by various groups across the US and display interesting
electron transport properties due to sub-5 nm spacing between iron
centered heme groups, as well as photoconductivity, which may allow for
a large variety of possible bionanoelectronics.
2. OmsZ cytochromes are relatively unexplored compared to OmcS and may
present some interesting opportunities.
3. There has been prior/current work on Geobacter memristors conducted by
Yao group at UMass Amherst and the same group showed that Geobacter
OmcS nanowires can serve as chemical sensors (so lateral devices may
also be interesting to fabricate).
4. Soil bacteria like G. sulfurreducens are highly abundant and relatively
easy to incubate so there may be no need for an E.coli expression system
during mass production. Another soil bacteria with cytochrome nanowires
that may be of interest for memristor applications is Shewanella
oneidensis (with OmcA and Mtrc cytochromes). Interestingly, both species
are known to be able to clean up pollutants and radioactive waste, which
may be incorporated in device fabrication processes to eliminate waste.
5. If nanowire monomers in vertical devices are arranged in a vertically
oriented fashion (like an upright barrel) unlike the horizontal orientation
used in Fu et al. Bioinspired bio-voltage memristors (2020, Yao group),
then may present other electrical properties and may not need dielectric to
serve a useful function (it will likely not be a memristor anymore).
6. As understanding of heme transport of electrons in nanowires improves,
possible scaling down of the devices to ~5 nm with 2D material electrodes
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and heme group sandwiched in between may be a possibility. However,
heme groups may still need to be embedded in dielectric.
- Disadvantages:
1. As far as current understanding goes, devices operate through cytochrome
catalysis of CBRAM redox reaction, so dielectric is necessary, limiting
how small devices can be scaled down.
2. Advantages 5 and 6 are purely speculative.
3. Isolation of individual nanowire monomers may be challenging.
4. Embedding monomers in dielectric material in a uniform manner is
finicky to the point of being nearly impossible. Though, because the
CBRAM redox reaction is catalyzed, I suppose we do have flexibility in
the choice of dielectric materials from an electrical engineering standpoint.
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Focus 2: AdEx CuI Memristor Crossbar Array with Optically Controlled Adaptability
One major focus within the memristor community is the prospect of crossbar arrays performing
in-memory computing through SNNs (Spiking Neural Networks) and are trained based on a
leaky integrate and fire (LIF) model, through the additional circuitry such as capacitors and/or
transistors to the crossbar array. SNNs that exhibit LIF behavior have their various downfalls
(consider that CMOS and capacitors are required, as well as the complexity of novel algorithms
required) and one way to compensate for this is by providing additional benefits through the
fabrication of a device that is capable of different spiking patterns on demand i.e. one that
follows the Adaptive Exponential Integrate and Fire (AdEx) model. Discussing the neuronal
dynamics behind integrate-and-fire models such as LIF and AdEx, and how it translates over to
learning in memristor circuits, is kinda cumbersome so I’ll leave it up to you to look it up on
your own if interested. I do warn that memristor LIF behavior is unfortunately very poorly
explained and I do not think there is one sole source online that helps in understanding even at
the basic level. You just have to read a lot. Memristor networks with AdEx behavior have
already been proven to display higher accuracy by a group in IIT Delhi (2020) Shaban,
Bezugam, Suri, An adaptive threshold neuron for recurrent spiking neural networks with
nanodevice hardware implementation. Unlike the previous IIT Delhi group I mentioned with the
Azurin device, this group’s work seems legitimate. I speculate that if adaptation could be
modulated with an additional input i.e. light stimulus, instead of peripheral circuitry, then
integrate-and-fire behavior in SNNs can be achieved with just one group or array of memristors.
Mishra et al. Light-Mediated Multi-Level Flexible Copper Iodide Resistive Random Access
Memory for Forming-Free, Ultra-Low Power Data Storage Application (Incheon National
University, South Korea, 2022) has shown CuI memristors are optically tunable, with good
retention and meh endurance (device can definitely be improved to increase in endurance). I
propose the fabrication of an ultrathin memristor crossbar array of the configuration Cu (10
nm)/CuI (10 nm)/ITO (10 nm) on a glass substrate though UV-lithography patterning and
sputtering all materials (Paine group has optimized sputter system for CuI. For CuI, you can also
use dissolution - recrystallization solution technique). It is important to note that I chose this
device because I thought it would be easy to fabricate with Brown University’s rather limited
nanoelectronics facilities, however, other optomemristors may be better suited for light mediated
AdEx behavior. After standard physical, chemical, and electrical characterization, LTP and
LTD/STDP measurements should be made (never recorded before for CuI memristor). Then
record all electrical characterization/learning behavior under illumination of various wavelengths
in the visible range. Finally, perform an image recognition task with crossbar arrays interfaced
with looped optical feedback to demonstrate application of adaptability in possibly decreasing
the amount of time required for image recognition, while maintaining high accuracy. If an AdEx
memristor crossbar array is interfaced with the right photonic device/network, I predict it would
lead to incredibly huge milestones for robotics, remote sensing, medical imaging, and modem
applications. AdEx experiments may be applicable to some biomemristors.
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Focus 3: Ising Machine via Memristor-based Autaptic Oscillator Circuit Array (MAOCA)
and Peripheral Memristor Coupling Network (MCN) i.e. MCN-MAOCA Ising Machine
Memristor crossbar arrays have been demonstrated to perform Probabilistic/Ising computing. An
Ising machine is a probabilistic computing platform that solves the 2D Ising problem first
proposed by Wilhelm Lenz to his Ph.D student Ernst Ising (the same Lenz all electricity &
magnetism students hate). The original problem essentially entails trying to figure out the spin
states (can either be +1 or -1) in a so called “spin glass” i.e. magnetic material with atoms or
magnetic domains that each have their own spin state based on how strongly coupled each spin
state is with their nearest neighbors in the system, denoted by coupling factor J
ij
. The theory
proposes that the spin states present in the system will arrange themselves in such a way that
they minimize the system’s total energy, given by the famous equation (without an external
magnetic field): , where σ
i
is the spin state (+1 or -1) and i and j correspond to
𝐻=
<𝑖,𝑗>
∑ 𝐽
𝑖𝑗
σ
𝑖
σ
𝑗
nearest neighbors for each spin state in the system. It wasn't until 20 years later that an analytic
solution was found for a simple square lattice by Onsager, and as of yet no one has managed to
find either a numerical or analytical solution for the 3D Ising problem. A common way to solve
the 2D Ising problem nowadays is numerically with the Metropolis-Hastings algorithm (a
Markov Monte Carlo method). Someone could try extending the circuit I speculate about later in
this passage into a 3D Ising Machine, which could have interesting implications for the statistical
mechanics behind ferromagnetism in addition to the field of probabilistic computing. There are
many important, so called NP-hard combinatorial optimization problems in computer science
that can be broken down into an Ising problem such as the famous Traveling Salesman Problem,
as well as the Max-Cut Problem which has become the standard demonstration for Ising
machines in the literature. A computing system that solves these combinatorial optimization
problems through breaking them down into an Ising problem and optimizes itself upon initial
stimulus and programmable J
ij
factors to solve for all spin states σ
i
in the system, thereby solving
the problem, is referred to as an Ising Machine. Many Ising Machines made in the past 10 years
make use of parametric oscillators i.e. using subharmonic injection (input wave signal of a given
frequency into a system of coupled oscillators that are oscillating at half the input frequency) to
phase lock a series of electrical (or optical) analog/wave signals to each other. This means when
the system is allowed to run for enough time to minimize its energy, all the output waveforms
will ideally be either in phase with each other (+1 spin state i.e phase shift of 0
o
) or out of phase
with each other (-1 state i.e. phase shift of 180
o
), and these output waveforms are essentially the
solution to our problem which can then be fed into peripheral circuitry for whatever is needed.
Having all oscillators be either in phase or exactly out of phase with each other is sometimes
referred to as phase bipartition. The overall minimization process is sometimes referred to as
annealing or quantum annealing (look up D-wave). However, one must be careful with how they
perform subharmonic injection or else the phase bipartition may never be achieved or rather than
phase bipartition individual oscillators may accidentally converge to random phases.
Additionally, it should be noted that the optimization process has a certain probability of
occurring, hence, an Ising machine is considered a type of probabilistic computing platform. I
completely understand if none of this makes sense, especially without visuals, but I can assure
you that despite my mention of quantum annealing, you do not actually need any knowledge of
quantum mechanics to understand Ising machines. I’m linking an excellent video playlist made
by Professor Aaron Danner and his colleagues at NUS that explains the power of Ising
computers in a way anyone from the general public can understand.
3/24/2024
https://www.youtube.com/watch?v=mD-0VpNSJA0&list=PLXb3r5ny8_1XxvRZtA1mM-vb-Pe
MGgc7a
So far, most memristor based Ising machines/Hopfield Neural Networks have yet to take full
advantage of memristors’ analog behavior and large parallelism (HNNs; an extension of Ising
model specific for neurons/computing. For all intentions and purposes of this doc, you can think
of Ising Machines and HNNs as the same thing). They usually perform Ising computing without
relying on oscillatory behavior. Most who work on memristor Ising machines also argue that
they outperform Ising machines that are based on oscillators, which is deeply questionable since
this is too small of a research area to begin with to make such statements. I speculate that
oscillator based Ising machines are the route to take for the time being given that the few
conduction value based memristor Ising machines face a significant drop in success probability
for larger problems due to device variation, as well as the fact that they have considerably lower
clock frequency than GPU and optical parametric oscillator counterparts. Rather than have
conduction states artificially create bipartition, I claim a more versatile memristor based Ising
machine can be achieved by using conduction states for solely programming coupling strengths
(J
ij
) and allowing for a separate memristor-capacitor based oscillator circuit to run computations.
However, proper subharmonic injection will inevitably always limit computing capabilities for
oscillatory Ising machines. Additionally, coupling elements (J
ij
) need to be highly reconfigurable
for solving larger and more complex systems practical applications require. Highly
reconfigurable J
ij
values would allow for one Ising machine to solve many different kinds of
combinatorial optimization problems instead of being limited to one specific problem of interest.
I propose one can create memristor-capacitor autaptic oscillator circuit arrays (MAOCA) that are
analogous to the Schmidtt trigger-like circuits presented in Vaidya et al. [1] in order to achieve
phase bipartition through feedback loops rather than external injection of a subharmonic current.
Output signals from the array will be fed into a peripheral memristor-based coupling network
(MCN) circuit before being fed back into the array as inputs to simultaneously maintain all-to-all
connectivity (which as of writing this, I think D-wave has yet to accomplish), and allow for
highly reconfigurable coupling strengths through a second set of inputs into the MCN.
Additionally, the MCN-MAOCA Ising Machine could be interfaced with a neuromorphic chip
that can pre-process or post-process data entering and exiting the Ising Machine. It should also
be noted that if someone managed to fabricate nanoscale CNT inductors with high enough
quality factors, an effort which appears to have been abandoned since the mid-2000s, then
memristor-capacitor oscillators in the MCN-MAOCA can be replaced with drastically simpler
and smaller circuits using memristors in series with inductors. Extensive AC characterization of
memristor-capacitor networks is likely needed before implementation but may reap some
additional benefits and lead to possible circuit simplifications. With all that said, this idea is still
very bare bones i.e. basically just pure speculation as an extension of the following works below:
1. Vaidya, Kanthi, Shukla. Creating electronic oscillator-based Ising machines without
external injection locking. Nat. Scientific Reports (2022)
2. Albertson, Rulsu. Highly reconfigurable oscillator‑based Ising Machine through
quasiperiodic modulation of coupling strength. Nat. Scientific Reports (2023)
3. Hoppensteadt, Izhikevich. Oscillatory Neurocomputers with Dynamic Connectivity.
Phys. Rev. Lett. (1999)
4. H. Li and K. Banerjee, High-Frequency Analysis of Carbon Nanotube Interconnects and
Implications for On-Chip Inductor Design, in IEEE (2013)
3/24/2024
5. Cai, Kumar, et al. Power-efficient combinatorial optimization using intrinsic noise in
memristor Hopfield neural networks. Nat. Electronics (2020)
6. Jiang et al. Efficient combinatorial optimization by quantum-inspired parallel annealing
in analogue memristor crossbar. Nat. Communications (2023)
7. Ying et al. Locally active memristor based oscillators: The dynamic route from period to
chaos and hyperchaos. Chaos (2021)
However, on the chance this is possible, MCN-MAOCA could result in a room temperature
analog computer capable of solving problems we are hoping we will eventually be able to solve
with developing quantum computing technology. Compared to quantum computers, it would be
drastically cheaper and more energy efficient for running computations. Given some time,
MCN-MAOCA could be optimized to meet reliability/accuracy standards and clock speeds (two
glaring bottlenecks) required for seamless integration into already existing CMOS technology,
including everyday handheld devices. As futuristic as this sounds, I believe this would be faster
to achieve than a useful quantum computer, which will probably only be accessible to select few
companies and governments for usage anyway rather than for the general public despite IBM’s
open source SDK Qiskit. I could also just be venting here because of how disappointed I was
when I used Qiskit myself back when I was more optimistic about quantum computing. Plus, I’m
also annoyed at how overshadowed the fields of Quantum Metrology and Sensing are by
Quantum Computing in mainstream media, since I believe the former fields mentioned will have
a much more significant impact on the general public within a reasonable time scale and with
drastically less resources required. Unfortunately, I doubt anyone is going to care too much about
probabilistic computing because all the stupid hype over the words “quantum computing”, and
“Ising Machine” just doesn’t sound as marketable. Maybe the MCN-MAOCA could be called
the Mc. Maoca? Who knows, maybe someone will come up with a photonic or neutral-atom
quantum computer that is capable of simultaneously achieving long coherence times, large
enough qubit counts for both running useful computations and error correction, and scalability,
so I could be full of crap. However, as of writing this, I am pretty unimpressed by the current
state of quantum computing and believe it may take 200 years from now before we get
something useful out of it, assuming the human race is still alive by then. I first encountered
probabilistic computing, the Ising Model/Machine, and Hopfield neural networks in my literature
reading around 1.5 years ago, but never fully understood how HNNs really worked until after I
took a course in statistical mechanics and read through some papers last summer. I kept this idea
buried in the back of my mind until my former lab PI brought up the idea of realizing an Ising
Machine with a memristor crossbar array about five months ago, and reminded me of its
potential and my previous thoughts. In addition to the potential societal impact described, the
MCN-MAOCA Ising Machine would have the more immediate impact of changing memristor
research on two fronts. First, it would demonstrate an actually useful analog computation
performed with a memristor crossbar array (which is surprisingly absent despite all the papers
claiming memristor crossbar arrays may bring about an era of analog computing, and then
proceed to either never input any AC voltage signals, use an AC voltage but at a fixed frequency,
or use AC voltage signals in very impractical frequency ranges). Second, it would provide
justification to pursue Ising Machines and other probabilistic computing avenues for memristors,
such as Bayesian Neural Networks (BNNs), with just as much enthusiasm as in-memory
computing.
3/24/2024
Misc. Focus: γ-Glycine Ferroelectric Crossbar Array
Through PFM experiments, γ-Glycine has demonstrated a measurable d33 value and interesting
helical texture of electric dipoles with net direction in z-axis (likely due to helical hydrogen
bonding network. See Hu et al. Bioferroelectric Properties of Glycine Crystals. J. Phys. Chem.
Lett. (2019) ). This phase of glycine is much more stable than the other phases (alpha and beta)
and prior piezoelectric γ-Glycine devices fabricated are on the order of microns thick, hence
unsuitable for memory applications. If someone was able to come up with a fabrication method
for a device of the configuration Cu/crystalline γ-Glycine/BE, such that γ-Glycine was grown on
the order of sub-100 nm in thickness (initial device; miniaturization possible). The BE (bottom
electrode) will ideally be transparent and serve as a substrate that γ-Glycine can be uniformly
deposited or grown on. This device could have very interesting implications for both data
storage/processing and photonic devices, given ferroelectrics are also capable of neuromorphic
computing and γ-Glycine displays interesting optical properties.
Super random aside from a personal experience that I think is worth bringing up. Once, I tried
discussing a sericin based memristor device I had in mind to a professor from another university.
I was kinda roasted (given the circumstances I probably deserved it) and told it would never
work despite there being two prior devices already published. Granted, I only fully trust the
device fabricated by Wang et al. Sericin for Resistance Switching Device with Multilevel
Nonvolatile Memory (2013) at Nanyang Tech in Singapore because Rong et al. Demonstration of
electronic synapses using a sericin-based bio-memristor (2023) barely specifies how their sericin
thin film was fabricated. I don’t blame this professor for their view on my idea and they brought
up a few fair points regarding my proposed device but they cut me off before I could even have a
chance to finish fully explaining. I remember they kept saying “the device would short” and they
didn’t see how it was “cutting edge” since CBRAM has already been researched a lot in the past.
I think what they might have meant to say was it would be an open circuit considering a pretty
common worry when first fabricating a biomemristor is nothing conducting at all due to the RS
layer being way too insulating. Ironically, a few months after this professor grilled me I came
across a paper on an interesting nanocone patterned fibroin CBRAM memristor that was
published in Advanced Materials. If fibroin memristors are still relevant, then sericin is by
default. The characterization seems pretty thorough and the device, in particular the fabrication
method, is definitely unique enough to be considered “cutting edge” in my opinion (though like
all device research, its practical applications are debatable). The paper is Li et al. Achieving
Reliable and Ultrafast Memristors via Artificial Filaments in Silk Fibroin (2023). I’m sure this
professor has no clue who I am but I hope they give the paper a read at some point. Even if they
don’t think it’s “cutting edge”, it’s definitely a fascinating device. Also, this method of confining
filamentation reminded me of work done in Oh et al. Area-Selective Atomic Layer Deposition for
Resistive Random-Access Memory Devices (2023) which I read about a month before.
I would like to finally note that I do not have any publications of my own and never got the
chance to successfully fabricate a device. I just happened to read a lot of papers. If you think I’m
just some idiotic undergrad who’s full of crap, I think that’s totally valid and completely get
where you’re coming from.
- Sritarun Chinta
